Semiconductor memory

ABSTRACT

A semiconductor memory according to an embodiment includes a first conductor, a first insulator and memory pillars. The first conductor and the first insulator are alternately stacked along a first direction. The memory pillars penetrates through the stacked first conductor and first insulator. Each of the memory pillars include a semiconductor, a tunnel insulating film, a second insulator, and a block insulating film. The memory pillars include a first memory pillar. The stacked first insulator includes a first layer and a second layer that are adjacent to each other in the first direction. The first conductor between the first layer and the second layer includes a first conductive part, a second conductive part, and a first dissimilar conductive part.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of and is based upon andclaims the benefit of priority from U.S. Ser. No. 16/261,939, filed onJan. 30, 2019, which is based upon and claims the benefit of priorityfrom Japanese Patent Application No. 2018-129771, filed Jul. 9, 2018,the entire contents of each of which are incorporated herein byreference.

FIELD

Embodiments relate to a semiconductor memory.

BACKGROUND

There is known an NAND-type flash memory that is capable of storing datain a nonvolatile manner.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a configuration example of asemiconductor memory according to an embodiment;

FIG. 2 is a circuit diagram illustrating an example of a circuitconfiguration of a memory cell array included in the semiconductormemory according to the embodiment;

FIG. 3 is a plane view of an example of a planar layout of the memorycell array included in the semiconductor memory according to theembodiment;

FIG. 4 is a cross-sectional view of an example of a cross-sectionstructure of the memory cell array included in the semiconductor memoryaccording to the embodiment;

FIG. 5 is a cross-sectional view of an example of a more detailedcross-section structure of the memory cell array included in thesemiconductor memory according to the embodiment;

FIGS. 6, 7, and 8 are cross-sectional views of an example of across-section structure of a memory pillar included in the semiconductormemory according to the embodiment;

FIGS. 9, 10, 11, 12, and 13 are cross-sectional views of the memory cellarray, illustrating an example of a manufacturing process of thesemiconductor memory according to the embodiment;

FIG. 14 is a more detailed cross-sectional view of the memory cellarray, illustrating the example of the manufacturing process of thesemiconductor memory according to the embodiment;

FIG. 15 is a cross-sectional view of the memory cell array, illustratingthe example of the manufacturing process of the semiconductor memoryaccording to the embodiment;

FIG. 16 is a more detailed cross-sectional view of the memory cellarray, illustrating the example of the manufacturing process of thesemiconductor memory according to the embodiment;

FIG. 17 is a cross-sectional view of the memory cell array, illustratingthe example of the manufacturing process of the semiconductor memoryaccording to the embodiment;

FIG. 18 is a more detailed cross-sectional view of the memory cellarray, illustrating the example of the manufacturing process of thesemiconductor memory according to the embodiment;

FIGS. 19, 20, 21, and 22 are cross-sectional views of the memory cellarray, illustrating the example of the manufacturing process of thesemiconductor memory according to the embodiment;

FIG. 23 is a more detailed cross-sectional view of the memory cellarray, illustrating the example of the manufacturing process of thesemiconductor memory according to the embodiment;

FIG. 24 is a cross-sectional view of the memory cell array, illustratingthe example of the manufacturing process of the semiconductor memoryaccording to the embodiment;

FIG. 25 is a more detailed cross-sectional view of the memory cellarray, illustrating the example of the manufacturing process of thesemiconductor memory according to the embodiment;

FIG. 26 is a cross-sectional view of the memory cell array, illustratingthe example of the manufacturing process of the semiconductor memoryaccording to the embodiment;

FIG. 27 is a cross-sectional view of an example of a cross-sectionstructure of a memory cell array included in a semiconductor memoryaccording to a comparative example of the embodiment;

FIG. 28 is a diagram illustrating an example of a formation process ofstacking wires in the semiconductor memory according to the comparativeexample of the embodiment;

FIG. 29 is a diagram illustrating an example of a formation process ofstacking wires in the semiconductor memory according to the embodiment;

FIG. 30 is a diagram illustrating an example of an advantage of a memorycell transistor in the semiconductor memory according to the embodiment;

FIG. 31 is a cross-sectional view of an example of a cross-sectionstructure of a memory cell array included in a semiconductor memoryaccording a modification example of the embodiment;

FIG. 32 is a cross-sectional view of an example of a cross-sectionstructure of a memory pillar included in the semiconductor memoryaccording to the modification example of the embodiment; and

FIG. 33 is a diagram illustrating an example of a formation process ofstacking wires in the semiconductor memory according to the modificationexample of the embodiment.

DETAILED DESCRIPTION

A semiconductor memory according to an embodiment includes a firstconductor, a first insulator and a plurality of memory pillars. Thefirst conductor and the first insulator are alternately stacked along afirst direction. The plurality of memory pillars penetrates through thestacked first conductor and first insulator. Each of the memory pillarsinclude a semiconductor along the first direction, a tunnel insulatingfilm that surrounds a side surface of the semiconductor, a secondinsulator that surrounds a side surface of the tunnel insulating film,and a block insulating film that surrounds a side surface of the secondinsulator. The memory pillars include a first memory pillar. The stackedfirst insulator includes a first layer and a second layer that areadjacent to each other in the first direction. The first conductorbetween the first layer and the second layer includes a first conductivepart, a second conductive part, and a first dissimilar conductive part.The first conductive part is in contact with the first layer and thesecond layer and widens along a second direction crossing the firstdirection. The second conductive part is provided between a blockinsulating film of the first memory pillar and the first conductivepart, is in contact with the block insulating film and the firstconductive part, and is formed from the same material as for the firstconductive part. The first dissimilar conductive part is a pair ofconductive parts that sandwiches the second conductive part along thefirst direction between the block insulating film of the first memorypillar and the first conductive part, and is formed from a materialdifferent from the material for the first conductive part and the secondconductive part.

Embodiments will be described below with reference to the drawings. Eachof the embodiments exemplifies a device or method of carrying out thetechnical ideas of the invention. The drawings are schematic orconceptual and thus the dimensions, ratios, and others illustrated inthe drawings may not necessarily be identical to the real ones. Thetechnical ideas of the present invention are not specified by theshapes, structures, layouts, and others of constituent elements.

In the following descriptions, the constituent elements withapproximately identical functions and configurations will be givenidentical reference signs. The numeral appended to a characterconstituting a reference sign is referred to by a reference signincluding the same character and is used to differentiate between theelements having similar configurations. Similarly, the characterappended to a numeral constituting a reference sign are referred to by areference sign including the same numeral and is used to differentiatebetween the elements having similar configurations. When there is noneed to differentiate between the elements indicated by the referencesigns including the same character or numeral, each of these elements isreferred to by the reference sign including only the character ornumeral.

[1] Embodiments

A semiconductor memory 1 according to an embodiment will be describedbelow.

[1-1] Configuration of the Semiconductor Memory 1

[1-1-1] Overall Configuration of the Semiconductor Memory 1

The semiconductor memory 1 is an NAND-type flash memory that is capableof storing data in a nonvolatile manner, for example. The semiconductormemory 1 is controlled by an external memory controller 2, for example.FIG. 1 illustrates a configuration example of the semiconductor memory 1according to the embodiment.

As illustrated in FIG. 1, the semiconductor memory 1 includes a memorycell array 10, a command register 11, an address register 12, asequencer 13, a driver module 14, a row decoder module 15, and a senseamplifier module 16, for example.

The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (nis an integer of 1 or larger). The block BLK is a set of a plurality ofmemory cells that is capable of storing data in a nonvolatile manner andis used as an erase unit of data, for example.

The memory cell array 10 has a plurality of bit lines and a plurality ofword lines. Each of memory cells is associated with one bit line and oneword line, for example. The detailed configuration of the memory cellarray 10 will be described later.

The command register 11 holds a command CMD received by thesemiconductor memory 1 from the memory controller 2. The command CMDincludes an order for causing the sequencer 13 to execute a readoperation, a write operation, an erase operation, or the like, forexample.

The address register 12 holds address information ADD received by thesemiconductor memory 1 from the memory controller 2. The addressinformation ADD includes a block address BA, a page address PA, and acolumn address CA, for example. For example, the block address BA, thepage address PA, and the column address CA are used to select the blockBLK, the word line, and the bit line, respectively.

The sequencer 13 controls the entire operations of the semiconductormemory 1. For example, the sequencer 13 controls the driver module 14,the row decoder module 15, the sense amplifier module 16, and others,based on the command CMD held in the command register 11 to execute aread operation, a write operation, an erase operation, or the like.

The driver module 14 generates a voltage to be used for a readoperation, a write operation, an erase operation, or the like. Thedriver module 14 applies the generated voltage to a signal linecorresponding to the selected word line, based on the page address PAheld in the address register 12, for example.

The row decoder module 15 selects one block BLK in the correspondingmemory cell array 10, based on the block address BA held in the addressregister 12. The row decoder module 15 transfers the voltage applied tothe signal line corresponding to the selected word line to the selectedword line in the selected block BLK, for example.

At a write operation, the sense amplifier module 16 applies a desiredvoltage to each of the bit lines according to write data DAT receivedfrom the memory controller 2. At a read operation, the sense amplifiermodule 16 determines the data stored in the memory cell based on thevoltage in the bit line, and transfers the determination result as readdata DAT to the memory controller 2.

Communications between the semiconductor memory 1 and the memorycontroller 2 comply with NAND interface standards, for example. Forexample, used for communications between the semiconductor memory 1 andthe memory controller 2 are a command latch enable signal CLE, anaddress latch enable signal ALE, a write enable signal WEn, a readenable signal REn, a ready busy signal RBn, and an input/output signalI/O.

The command latch enable signal CLE is a signal indicating that theinput/output signal I/O received by the semiconductor memory 1 is thecommand CMD. The address latch enable signal ALE is a signal indicatingthat the signal I/O received by the semiconductor memory 1 is theaddress information ADD. The write enable signal WEn is a signal forordering the semiconductor memory 1 to input the input/output signalI/O. The read enable signal REn is a signal for ordering thesemiconductor memory 1 to output the input/output signal I/O.

The ready busy signal RBn is a signal for notifying the memorycontroller 2 of whether the semiconductor memory 1 is in a ready statewhere to accept an order from the memory controller 2 or in a busy statewhere not to accept an order. The input/output signal I/O is an 8-bitsignal that can include the command CMD, the address information ADD,the data DAT, and others, for example.

The semiconductor memory 1 and the memory controller 2 described abovemay constitute one semiconductor device in combination. Examples of sucha semiconductor device include a memory card such as SD™ card, a solidstate drive (SSD), and others.

[1-1-2] Circuit Configuration of the Memory Cell Array 10

FIG. 2 illustrates an example of a circuit configuration of the memorycell array 10 included in the semiconductor memory 1 according to theembodiment, extracting one block BLK from the plurality of blocks BLKincluded in the memory cell array 10.

As illustrated in FIG. 2, the block BLK includes four string units SU0to SU3, for example. Each of the string units SU includes a plurality ofNAND strings NS.

The NAND strings NS are associated with bit lines BL0 to BLm (m is aninteger of 1 or larger). Each of the NAND strings NS includes memorycell transistors MT0 to MT7 and select transistors ST1 and ST2.

Each of the memory cell transistors MT includes a control gate and acharge accumulation layer to hold data in a nonvolatile manner. Theselect transistors ST1 and ST2 are used to select the string unit SU andthe block BLK at the time of various operations.

In each of the NAND strings NS, the memory cell transistors MT0 to MT7are connected in series between the select transistors ST1 and ST2. Inthe same block BLK, the control gates of the memory cell transistors MT0to MT7 are respectively connected in common to the word lines WL0 toWL7.

In each of the NAND strings NS, the drain of the select transistor ST1is connected to the associated bit line BL, and the source of the selecttransistor ST1 is connected to one each end of the memory celltransistors MT0 to MT7 connected in series. In the same block BLK, thegates of the select transistors ST1 in the string units SU0 to SU3 arerespectively connected in common to the select gate lines SGD0 to SGD3.

In each of the NAND strings NS, the drain of the select transistor ST2is connected to the other ends of the memory cell transistors MT0 to MT7connected in series. In the same block BLK, the sources of the selecttransistors ST2 are connected in common to the source line SL, and thegates of the select transistors ST2 are connected in common to theselect gate line SGS.

In the circuit configuration of the memory cell array 10 describedabove, the bit lines BL are connected in common between the plurality ofNAND strings NS corresponding to the blocks BLK, for example. The sourceline SL is connected in common between the plurality of blocks BLK, forexample.

A set of the plurality of memory cell transistors MT connected to thecommon word line WL in one string unit SU is called cell unit CU, forexample. For example, the storage capacity of the cell unit CU includingthe memory cell transistors MT storing one each bit data is defined as“one page data”, for example. The cell unit CU can have a storagecapacity of two page data or more according to the bit count of the datastored in the memory cell transistors MT.

The circuit configuration of the memory cell array 10 included in thesemiconductor memory 1 according to the embodiment is not limited to theconfiguration described above. For example, the numbers of the memorycell transistors MT and the select transistors ST1 and ST2 included ineach of the NAND strings NS can be designed to arbitrary numbers. Thenumber of the string units SU included in each of the blocks BLK can bedesigned to an arbitrary number.

[1-1-3] Structure of the Memory Cell Array 10

An example of a structure of the memory cell array 10 in the embodimentwill be described below.

In the drawings referred to below, an X direction corresponds to thedirection of extension of the word line WL, a Y direction corresponds tothe direction of extension of the bit line BL, and a Z directioncorresponds to the direction perpendicular to the surface of asemiconductor substrate 20 on which the semiconductor memory 1 isformed.

In the cross-sectional views referred to below, illustration ofconstituent elements such as insulating layers (inter-layer insulatingfilms), wires, and contacts are omitted as appropriate for the sake ofvisibility. The planar views have hatching added as appropriate for thesake of visibility. The hatching added to the planar views is notnecessarily related to the materials and characteristics of theconstituent elements with the hatching.

FIG. 3 illustrates an example of a planar layout of the memory cellarray 10 included in the semiconductor memory 1 according to theembodiment, extracting structural bodies corresponding to the stringunits SU0 and SU1.

As illustrated in FIG. 3, a region with the memory cell array 10includes a plurality of slits SLT, a plurality of string units SU, and aplurality of bit lines BL, for example.

The plurality of slits SLT extends in the X direction and is arrayed inthe Y direction. One string unit SU is disposed between the slits SLTadjacent to each other in the Y direction, for example.

Each of the string units SU includes a plurality of memory pillars MP.The plurality of memory pillars MP is disposed in a staggered patternalong the X direction, for example. Each of the memory pillars MPfunctions as one NAND string NS, for example.

The plurality of bit lines BL extends in the Y direction and is arrayedin the X direction. For example, the bit lines BL are disposed in such amanner as to overlap at least one memory pillar MP in each of the stringunits SU. Specifically, two bit lines BL overlap each of the memorypillars MP, for example.

Out of the plurality of bit lines BL overlapping the memory pillars MP,a contact CP is provided between one bit line BL and the memory pillarMP. Each of the memory pillars MP is electrically connected to thecorresponding bit line BL via the contact CP.

The number of the string units SU provided between the adjacent slitsSLT can be arbitrarily designed. The number and layout of the memorypillars MP illustrated in FIG. 3 are a mere example and the memorypillars MP can be designed to arbitrary number and layout. The number ofthe bit lines BL overlapping each of the memory pillars MP can bearbitrarily designed.

FIG. 4 is a cross-sectional view of FIG. 3 taken along line IV-IV,illustrating an example of a cross-section structure of the memory cellarray 10 included in the semiconductor memory 1 according to theembodiment.

As illustrated in FIG. 4, the region with the memory cell array 10includes conductors 21 to 25, the memory pillars MP, the contact CP, andthe slit SLT.

Specifically, the conductor 21 is provided above the semiconductorsubstrate 20 with an insulating layer therebetween. For example, theconductor 21 is formed in a plate shape widened along an XY plane and isused as source line SL. The conductor 21 contains polysilicon (Si), forexample.

Although not illustrated, a circuit such as the sense amplifier module16 is provided in a region between the semiconductor substrate 20 andthe conductor 21, for example.

The conductor 22 is provided above the conductor 21 with an insulatinglayer therebetween. For example, the conductor 22 is formed in a plateshape widened along the XY plane and is used as select gate line SGS.The conductor 22 contains polysilicon (Si), for example.

Insulating layers and the conductors 23 are alternately stacked abovethe conductor 22. For example, the conductors 23 are formed in a plateshape widened along the XY plane. The plurality of stacked conductors 23is used as word lines WL0 to WL7 in sequence from the semiconductorsubstrate 20 side. The conductors 23 contain tungsten (W), for example.

The conductor 24 is provided above the top conductor 23 via aninsulating layer therebetween. For example, the conductor 24 is formedin a plate shape widened along the XY plane and is used as select gateline SGD. The conductor 24 contains polysilicon (Si), for example.

The conductors 25 are provided above the conductor 24 with an insulatinglayer therebetween. For example, the conductors 25 are formed in a lineshape extended along the Y direction and are used as bit lines BL. Thatis, the plurality of conductors 25 is aligned along the X direction in aregion not illustrated. The conductors 25 contain copper (Cu), forexample.

The memory pillars MP are formed in a columnar shape extended along theZ direction and penetrate through the conductors 22 to 24, for example.Specifically, the upper end of each of the memory pillars MP is includedin a layer between the layer with the conductor 24 and the layer withthe conductors 25, for example. The lower end of each of the memorypillars MP is included in the layer with the conductor 21, for example.

Each of the memory pillars MP includes a core member 30, a semiconductor31, and a stacking film 32, for example.

The core member 30 is formed in a columnar shape extended along the Zdirection. The upper end of the core member 30 is included in a layerabove the layer with the conductor 24, for example. The lower end of thecore member 30 is included in the layer with the conductor 21, forexample. The core member 30 contains an insulator such as silicon oxide(SiO₂), for example.

The core member 30 is covered with the semiconductor 31. Thesemiconductor 31 is in contact with the conductor 21 via the sidesurface of the memory pillar MP. The semiconductor 31 is polysilicon(Si), for example. The stacking film 32 covers the side surface andbottom surface of the semiconductor 31 except for the portion of contactbetween the conductor 21 and the semiconductor 31.

The columnar contact CP is provided on the semiconductor 31. Oneconductor 25, that is, one bit line BL is in contact with the uppersurface of the contact CP. The memory pillar MP and the conductor 25 maybe electrically connected via two or more contacts or may beelectrically connected via any other wiring.

The slit SLT is formed in a plate shape extended along the Z directionto divide the conductors 22 to 24, for example. Specifically, the upperend of the slit SLT is included in a layer between the layer includingthe upper end of the memory pillar MP and the layer with the conductors25, for example. The lower end of the slit SLT is included in the layerwith the conductor 21, for example.

An insulator 40 is provided in the slit SLT. The insulator 40 containsan insulating material such as silicon oxide (SiO₂), for example. Theinsulator 40 may be formed from a plurality of kinds of insulatingmaterials. For example, before silicon oxide is embedded in the slitSLT, silicon nitride (SiN) may be formed as a side wall of the slit SLT.

In the configuration of the memory pillars MP described above, theportion of intersection between the memory pillars MP and the conductor22 functions as select transistor ST2, for example. The portions ofintersection between the memory pillars MP and the conductors 23function as memory cell transistors MT. The portion of intersectionbetween the memory pillars MP and the conductor 24 functions as selecttransistor ST1. That is, the semiconductor 31 functions as channels forthe memory cell transistors MT and the select transistors ST1 and ST2.

FIG. 5 is a detailed cross-sectional view of the memory cell array 10included in the semiconductor memory 1 according to the embodiment,extracting a wiring layer with one word line WL and two insulatinglayers INS sandwiching the wiring layer.

As illustrated in FIG. 5, the memory pillar MP includes a convex portionTP in the wiring layer with the word line WL. Specifically, in a partpenetrating through the word line WL, the memory pillar MP has a portionsandwiched between the two insulating layers INS sandwiching the wordline WL.

The stacking film 32 in the memory pillar MP includes a tunnel oxidefilm 33, an insulating film 34, and block insulating films 35 and 36,for example.

The tunnel oxide film 33 is provided to cover the side surface andbottom surface of the semiconductor 31. The insulating film 34 isprovided to cover the side surface and bottom surface of the tunneloxide film 33. The insulating film 34 is used as a charge accumulationlayer of the memory cell transistor MT. The insulating film 34 containssilicon nitride (SiN), for example.

The block insulating film 35 is provided to cover the side surface andbottom surface of the insulating film 34. The block insulating film 36is provided to cover the side surface and bottom surface of the blockinsulating film 35. The block insulating film 35 contains silicon oxide(SiO₂), for example. The block insulating film 36 contains aluminumoxide (Al₂O₃), for example.

Each of the conductors 23 used as word line WL includes conductive parts50 to 52, for example.

The conductive parts 50 and 51 are provided on the side surface of theblock insulating film 36. Specifically, each of the conductors 23 isprovided with the conductive part 51 in contact with the upperinsulating layer INS and the block insulating film 36, the conductivepart 51 in contact with the lower insulating layer INS and the blockinsulating film 36, and the conductive part 50 that is sandwichedbetween the upper conductive part 51 and the lower conductive part 51 inthe wiring layer and is in contact with the block insulating film 36.

The conductive part 50 contains tungsten (W), for example. Theconductive parts 51 contain titanium nitride (TiN), for example, and areused as barrier metal in the manufacturing process of the semiconductormemory 1. In the semiconductor memory 1 according to the embodiment, theconductive part 50 and the conductive parts 51 are provided only nearthe outer periphery of the memory pillar MP.

Specifically, in a cross section parallel to the surface of thesemiconductor substrate 20 and including the conductive part 50, thedistance between the center of the memory pillar MP and the portion ofthe conductive part 50 in contact with the memory pillar MP and mostdistant from the memory pillar MP is shorter than half of the distance(MP pitch) between the centers of the adjacent memory pillars MP.

Similarly, in a cross section parallel to the surface of thesemiconductor substrate 20 and including the conductive part 51, thedistance between the center of the memory pillar MP and the portion ofthe conductive part 51 in contact with the memory pillar MP and mostdistant from the memory pillar MP is shorter than half of the distance(MP pitch) between the centers of the adjacent memory pillars MP.

The conductive part 52 is provided on the side surfaces of theconductive parts 50 and 51. Specifically, the conductive part 52 isprovided to be widened along the XY plane in a region with the conductor23 except for a region with the conductive parts 50 and 51, for example.In the semiconductor memory 1 according to the embodiment, theconductive part 52 is in contact with the upper insulating layer INS andthe lower insulating layer INS. The conductive part 52 contains tungsten(W), for example, and contains the same metal material as that for theconductive parts 50.

Describing in other words the structure of the conductor 23 (theconductive parts 50 to 52) explained above, the conductive part 52between the upper insulating layer INS and the lower insulating layerINS is a conductive part that is in contact with the upper insulatinglayer INS and the lower insulating layer INS and is widened along the XYplane. The conductive part 50 is a conductive part that is providedbetween the block insulating film 36 and the conductive part 52 of thememory pillar MP, is in contact with the block insulating film 36 andthe conductive part 52, and is formed from the same material as that forthe conductive part 52. The conductive parts 51 are a pair of conductiveparts that is provided between the block insulating film 36 and theconductive part 52 of the memory pillar MP to sandwich the conductivepart 50 along the Z direction, for example, and are dissimilarconductive part that is formed from a material different from that forthe conductive parts 50 and 52.

The conductive part 52 has a seam SE1 extending in the Z directionbetween the adjacent memory pillars MP, for example. In this way, theseam SE1 is vertically formed in the semiconductor memory 1 according tothe embodiment. The region of the seam SE1 may or may not contain an airgap.

The conductive part 52 has no seam formed in the region between thememory pillar MP and the slit SLT. An end portion EP of the conductivepart 52 provided between the memory pillar MP and the slit SLT may ormay not be in contact with the slit SLT portion. That is, the insulator40 in the slit SLT may have a portion sandwiched between the upperinsulating layer INS and the lower insulating layer INS.

An example of a structure of the memory pillar MP in a cross sectionparallel to the surface of the semiconductor substrate 20 will bedescribed below with reference to FIGS. 6, 7, and 8. FIG. 6 is across-sectional view of FIG. 5 taken along line VI-VI, illustrating anexample of a cross-section structure of the memory pillar MP and theword line WL in the layer including the conductive part 50. FIG. 7 is across-sectional view of FIG. 5 taken along line VII-VII, illustrating anexample of a cross-section structure of the memory pillar MP and theword line WL in the layer including the conductive parts 51. FIG. 8 is across-sectional view of FIG. 5 taken along line VIII-VIII, illustratingan example of a cross-section structure of the memory pillar MP in thelayer including the insulating layer INS.

As illustrated in FIG. 6, the core member 30 in the layer including theconductive part 50 is provided in the center of the memory pillar MP.The semiconductor 31 surrounds the side surface of the core member 30.The tunnel oxide film 33 surrounds the side surface of the semiconductor31. The insulating film 34 surrounds the side surface of the tunneloxide film 33. The block insulating film 35 surrounds the side surfaceof the insulating film 34. The block insulating film 36 surrounds theside surface of the block insulating film 35. The conductive part 50surrounds the side surface of the block insulating film 36. Theconductive part 52 surrounds the side surface of the conductive part 50.

As illustrated in FIG. 7, the structure of the memory pillar MP in thelayer including the conductive parts 51 is the same as the structure ofthe memory pillar MP described above with reference to FIG. 6. Theconductive parts 51 surround the side surface of the block insulatingfilm 36. The conductive part 52 surrounds the side surface of theconductive parts 51.

As illustrated in FIG. 8, the structure of the memory pillar MP in thelayer including the insulating layers INS is the same as the structureof the memory pillar MP described above with reference to FIG. 6. Theinsulating layers INS surround the side surface of the block insulatingfilm 36.

In the structure of the memory cell array 10 described above, the numberof the conductors 23 is designed based on the number of the word linesWL. A plurality of conductors 22 provided on a plurality of layers maybe assigned as select gate lines SGS. In the case where the select gatelines SGS are provided on the plurality of layers, conductors differentfrom the conductors 22 may be used. A plurality of conductors 24provided in a plurality of layers may be assigned as select gate linesSGD.

[1-2] Method of Manufacturing the Semiconductor Memory 1

FIGS. 9 to 26 illustrate an example of a cross-section structure of astructural body corresponding to the memory cell array 10 in amanufacturing process of the semiconductor memory 1 according to thefirst embodiment. An example of a series of manufacturing steps fromformation of the source lines SL to formation of the insulator 40 in theslit SLT will be described below in sequence with reference to FIGS. 9to 26.

First, a stacked structure corresponding to the source line SL is formedas illustrated in FIG. 9. Specifically, an insulating layer 60 is formedon the semiconductor substrate 20. Although not illustrated, circuitssuch as the row decoder module 15 and the sense amplifier module 16 areformed in the insulating layer 60.

Then, a conductor 61, a sacrificial member 62, a conductor 63, and aninsulating layer 64 are formed in sequence on the insulating layer 60.Each of the conductors 61 and 63 contains polysilicon (Si), for example.The material selected for the sacrificial member 62 is capable ofincreasing the etch selectivity for each of the conductors 61 and 63.

The wiring layer with the conductor 61, the sacrificial member 62, andthe conductor 63 in this step has a set of conductors to be used assource line SL in a step described later.

Next, a conductor 65 and a plurality of sacrificial members 67 arestacked as illustrated in FIG. 10. Specifically, the conductor 65 isformed on the insulating layer 64. Insulating layers 66 and thesacrificial members 67 are alternately stacked on the conductor 65. Aninsulating layer 68 is formed on the top sacrificial member 67.

The number of layers with the sacrificial members 67 corresponds to thenumber of layers of the word lines WL and the select gate lines SGD tobe stacked, for example. The conductor 65 contains polysilicon (Si), forexample. The conductor 65 corresponds to the conductor 22 describedabove with reference to FIG. 4, for example, and is used as select gateline SGS. Each of the insulating layers 66 and 68 contains silicon oxide(SiO₂), for example. The sacrificial members 67 contain silicon nitride(SiN), for example.

Next, memory holes MH are formed as illustrated in FIG. 11.Specifically, first, a mask with regions opened for formation of thememory pillars MP is formed on the insulating layer 68 byphotolithography or the like. In addition, the formed mask is used toexecute anisotropic etching to form the memory holes MH.

In the etching of this step, the memory holes MH penetrate through theinsulating layer 68, the plurality of sacrificial members 67, theplurality of insulating layers 66, the conductor 65, the insulatinglayer 64, the conductor 63, and the sacrificial member 62. The bottomportions of the memory holes MH are stopped in the layer with theconductor 61, for example. The method of etching in this step isreactive ion etching (RIE), for example.

In the etching of this step, the conductor 65 may be used as an etchingstopper. Using the conductor 65 as an etching stopper makes it possibleto suppress excessive entry of the bottom portion of the memory hole MHinto the conductor 61 and suppress fluctuation in the positions of thebottom portions of the plurality of memory holes MH.

Next, the sacrificial members 67 are partially removed via the memoryholes MH as illustrated in FIG. 12. The amount of removal of thesacrificial members 67 is adjusted such that the adjacent memory holesMH are not connected to each other via a space formed by removal of thesacrificial members 67, for example. In other words, the amount ofremoval of the sacrificial members 67 is adjusted such that thesacrificial members 67 provided between the adjacent memory holes MH arenot completely removed.

The method of removing the sacrificial members 67 in this step is wetetching, for example. Hereinafter, the space formed by removal of thesacrificial members 67 in this step will be called concave portion HE ofthe memory hole MH.

Next, a metal film 69 is formed in the memory holes MH and on theinsulating layer 68 as illustrated in FIG. 13. The metal film 69contains the conductive parts 50 and 51 as illustrated in FIG. 14. Inthis step, the conductive parts 51 and the conductive parts 50 areformed in sequence.

The conductive parts 51 are formed along the concave portions HE. Eachof the conductive parts 50 formed in the concave portion HE in this stephas a portion sandwiched between a portion of the conductive part 51 incontact with the upper insulating layer 66 and a portion of theconductive part 51 in contact with the lower insulating layer 66 out ofthe adjacent insulating layers 66.

In this step, the conductive parts 51 are used as barrier metal forformation of the conductive parts 50, for example. Specifically, at theformation of the conductive parts 50 (for example, tungsten), theconductive parts 51 suppress injection of impurities into the insulatinglayers 66 and the like to improve the adherence of the formed conductiveparts 50, for example.

Next, the metal film 69 is removed from the memory holes MH and theinsulating layer 68 except for part of the concave portions HE asillustrated in FIG. 15. The metal film 69 left in the concave portionsHE contains the conductive parts 50 and 51 as illustrated in FIG. 16.For example, the distance between the surface of the metal film 69exposed in the concave portion HE in this step and the center of thememory hole MH is wider than the distance between the surface of theinsulating layer 66 in contact with the memory hole MH and the center ofthe memory hole MH.

Next, the memory pillars MP are formed in the memory holes MH, and aninsulating layer 70 is formed on the upper surface of the structuralbody formed on the semiconductor substrate 20 as illustrated in FIG. 17.Specifically, for example, the stacking film 32 (the block insulatingfilms 36 and 35, the insulating film 34, and the tunnel oxide film 33),the semiconductor 31, and the core member 30 are formed in this order onthe upper surface of the insulating layer 68 and the inner walls of thememory holes MH.

After that, the core member 30, the semiconductor 31, and the stackingfilm 32 are removed from the layer above the upper surface of theinsulating layer 68, and the core member 30 is removed from the portionsabove the memory holes MH. The “portions above the memory holes MH”correspond to the portions included in the layer above the upper surfaceof the top sacrificial member 67. Then, the semiconductor 31 is formedin each of the memory holes MH in a region from which the core member 30is removed, and the insulating layer 70 is formed on the upper surfaceof the structural body formed on the semiconductor substrate 20.

Each of the memory pillars MP formed in this step has the convex portionTP and the block insulating film 36 provided at the convex portion TP incontact with the metal film 69 as illustrated in FIG. 18.

Next, the slits SLT are formed as illustrated in FIG. 19. Specifically,first, a mask with regions opened for formation of the slits SLT isformed on the insulating layer 70 by photolithography or the like. Inaddition, the formed mask is used to execute anisotropic etching to formthe slits SLT.

In the etching of this step, the slits SLT penetrate through theinsulating layer 70, the insulating layer 68, the plurality ofsacrificial members 67, the plurality of insulating layers 66, theconductor 65, the insulating layer 64, the conductor 63, and thesacrificial member 62. The bottom portions of the slits SLT are stoppedin the layer with the conductor 61, for example. The bottom portions ofthe slits SLT reach at least the layer with the sacrificial member 62.The method of etching in this step is reactive ion etching (RIE), forexample.

Next, the sacrificial member 62 is selectively removed by etching viathe slits SLT as illustrated in FIG. 20. Subsequently, the stackingfilms 32 provided on the side surface of the memory pillars MP arepartially removed via the region from which the sacrificial member 62 isremoved.

As a result, the semiconductors 31 in the memory pillars MP are exposedin the layer from which the sacrificial member 62 is removed. The methodof removing the sacrificial member 62 in this step is wet etching usinga water solution with selectivity of the sacrificial member 62 largerthan selectivity of the conductors 61 and 63, for example.

Next, a conductor 71 is formed as illustrated in FIG. 21. Specifically,the conductor 71 is formed by chemical vapor deposition (CVD), forexample, in the space from which the sacrificial member 62 is removed,and then is etched back.

As a result, the semiconductor 31 in each of the memory pillars MP and aset of the conductors 61, 71, and 63 are electrically connectedtogether. The set of the conductors 61, 71, and 63 corresponds to theconductor 21 described above with reference to FIG. 4, for example, andis used as source line SL. As the conductor 71, polysilicon doped withphosphorous is formed, for example.

Next, the sacrificial members 67 are removed as illustrated in FIG. 22.Specifically, first, the surfaces of the conductors 61, 71, 63, and 65(for example, polysilicon) exposed in the slits SLT are oxidized to forman oxide protective film not illustrated.

Then, the sacrificial members 67 are removed by wet etching with hotphosphoric acid, for example. The three-dimensional structure of thestructural body from which the sacrificial members 67 were removed ismaintained by the plurality of memory pillars MP, for example.

In this step, the metal film 69 is partially removed by etching via theslits SLT as illustrated in FIG. 23. Specifically, on the metal film 69near the convex portions TP, the conductive parts 51 are partiallyremoved via the regions from which the sacrificial members 67 wereremoved to expose the conductive parts 50.

Next, the conductive parts 52 are formed in the spaces from which thesacrificial members 67 were removed as illustrated in FIG. 24.Specifically, the metal material included in the conductive parts 50 isselectively grown (re-grown) by selective chemical vapor deposition(CVD), for example, as illustrated in FIG. 25. As a result, theconductive parts 52 grow from the surfaces of the conductive parts 50 toform the conductive parts 52.

In this step, each of the conductive parts 52 is in contact between theadjacent memory pillars MP, for example, and is grown such that the endportion EP of the conductive part 52 reaches the vicinity of the slitSLT. The position of the end portion EP of the conductive part 52 can bedesigned to an arbitrary position as far as the end portion EP at leastdoes not cause a short-circuit between the conductive parts 52 providedon the adjacent wiring layers.

As described above, the conductive parts 52 are metal wires formed byre-growing the conductive parts 50. The conductive parts 50 and theconductive parts 52 are formed by different methods and thus may bedifferent in grain size. Boundaries between the conductive part 50 andthe conductive part 52 can be formed. The sets of the conductive parts50 to 52 formed in the plurality of wiring layers in this step are usedas word lines WL or select gate line SGD, for example.

Next, the insulators 40 are formed in the slits SLT as illustrated inFIG. 26. In this step, before the insulators 40 are embedded in theslits SLT, silicon nitride or the like may be formed as side walls ofthe slits SLT.

In the manufacturing steps described above, the NAND strings NS, thesource line SL and the select gate lines SGS and SGD, and the word linesWL connected to the NAND strings NS are formed. Hereinafter, a processfor replacing the sacrificial members 67 with the conductive part 52will be called wiring replacement process, for example.

The manufacturing steps described above are a mere example and othersteps may be inserted into the manufacturing steps. For example, whenthe selectivity for selectively forming the conductive parts 52 issmall, an etch back step may be inserted after the steps described abovewith reference to FIGS. 24 and 25 to remove the metal or the like thatcould have been formed in the slits SLT.

[1-3] Advantageous Effects of the Embodiment

According to the semiconductor memory 1 in the embodiment, it ispossible to reduce a resistance value of the word line WL in thesemiconductor memory 1. Hereinafter, the advantageous effects of thesemiconductor memory 1 in the embodiment will be described in detailwith reference to a comparative example.

FIG. 27 illustrates an example of a cross-section structure of a memorycell array included in a semiconductor memory according to thecomparative example of the embodiment. As illustrated in FIG. 27, thecross-section structure of the memory cell array in the comparativeexample is different from the cross-section structure of the memory cellarray 10 in the embodiment in the structures of the memory pillars MPand the slits SLT and in the structure of the conductors correspondingto the word lines WL.

Specifically, in the semiconductor memory according to the comparativeexample, the block insulating films 36 and the conductive parts 51 areformed in the wiring replacement process, not at the time of formationof the memory pillars MP. Accordingly, the block insulating films 36 areomitted from the memory pillars MP in the comparative example, unlikethe memory pillars MP in the embodiment.

In the semiconductor memory according to the comparative example, theconductive parts 51 are formed in the wiring replacement process usingthe slits SLT, and the process for forming the concave portions HE inthe memory holes MH and leaving the metal film 69 in the concaveportions HE is not performed unlike in the embodiment, for example.Accordingly, the memory pillars MP in the comparative example do nothave the convex portions TP that are included in the memory pillars MPin the embodiment, for example.

In addition, the conductive parts 52 in the semiconductor memory in thecomparative example are formed on the surfaces of the barrier metal (theconductive parts 51) by chemical vapor deposition (CVD), for example,and a lateral seam SE2 is formed instead of the vertical seam SE1 in theembodiment. In the comparative example, the seam SE2 is formed not onlybetween the adjacent memory pillars MP but also between the memorypillar MP and the slit SLT. The seam SE2 formed between the memorypillar MP and the slit SLT is in contact with the insulator 40 formed inthe slit SLT, for example.

FIG. 28 illustrates an example of a process of formation of theconductive parts 52 in the wiring replacement process using the slit SLTin the semiconductor memory according to the comparative example of theembodiment. Hereinafter, a portion from which the sacrificial members 67are removed and that is in contact with the slit SLT will be calledopening portion OP.

As illustrated in FIG. 28(1), in the comparative example, after theremoval of the sacrificial members 67, the block insulating films 36 andthe conductive parts 51 are formed in sequence. Subsequently, theconductive parts 52 are formed. In this step, the conductive parts 52are formed on the surfaces of the conductive parts 51 as illustrated inFIG. 28(2).

As the step proceeds, the entire spaces where the sacrificial members 67were once formed are filled with the grown conductive parts 52, forexample, as illustrated in FIG. 28(3). After that, the conductive parts52 are removed from the slit SLT by etching, and the conductive parts 52adjacent in the stacking direction are electrically insulated asillustrated in FIG. 28(4).

In the process of formation of the conductive parts 52 described above,the conductive parts 52 grown from the upper side and the lower side arein contact with each other at the opening portion OP to close theopening portion OP, and the growth of the conductive parts 52 is stoppedinside the memory cell array.

In the comparative example, for example, in the wiring replacementprocess, the opening portion OP is closed before the conductive parts 52are embedded between the memory pillars MP to produce the possibility ofimperfect embedding of the conductive parts 52 between the memorypillars MP. When the embedding of the conductive parts 52 becomesimperfect, there is a possibility that the volume of the conductiveparts 52 to be formed will reduce to raise a wiring resistance.

In contrast, in the semiconductor memory 1 according to the embodiment,before the execution of the wiring replacement process using the slitSLT, the sacrificial members 67 are partially removed using the memoryholes MH to form the conductive parts 50 and 51. Then, the memorypillars MP including the block insulating film 36 are formed, and afterthe formation of the slits SLT, the selective growth of the conductiveparts 52, that is, the re-growth of the conductive parts 50 is executed.

FIG. 29 illustrates an example of a process of formation of theconductive parts 52 in the wiring replacement process using the slit SLTin the semiconductor memory 1 according to the embodiment.

As illustrated in FIG. 29(1), in the embodiment, when the sacrificialmembers 67 are removed via the slit SLT, the conductive parts 50 and 51are formed between the opening portion OP and the block insulating film36 of the memory pillar MP.

In the embodiment, the conductive parts 52 are formed by selectivelygrowing (re-growing) a metal material included in the conductive parts50. Accordingly, in this step, the conductive parts 52 grow laterallyfrom the surfaces of the conductive parts 50 as illustrated in FIG.29(2). In the process of growth, the conductive parts 52 are in contactwith the insulating layers adjacent to the wiring layers.

As the process proceeds, the grown conductive part 52 reaches near theopening portion OP, for example, and the conductive parts 52 grownbetween the adjacent memory pillars MP are in contact with each other,as illustrated in FIG. 29(3). Accordingly, in the embodiment, the entirespaces where the sacrificial members 67 were once formed are filled withthe grown conductive parts 52, for example.

In this manner, in the semiconductor memory 1 according to theembodiment, the conductive parts 52 are formed by selective growth.Accordingly, in this step, it is possible to suppress the formation ofthe conductive parts 52 on the side surface portions of the slits SLT orthe surface of the structural body formed on the semiconductor substrate20.

As described above, in the semiconductor memory 1 according to theembodiment, the sacrificial members 67 are partially replaced with theconductive parts 50 via the memory holes MH to allow the use ofselective growth as a method of forming the conductive parts 52 via theslits SLT.

In addition, in the semiconductor memory 1 according to the embodiment,the use of selective growth does not allow the opening portion OP to beclosed at the formation of the conductive parts 52 as in the comparativeexample, thereby achieving improvement in the embedding property of theconductive parts 52.

Further, in the semiconductor memory 1 according to the embodiment, atthe execution of the wiring replacement process using the slits SLT, theblock insulating films 36 and the conductive parts 51 are not formed tomake the volume of the conductive parts 52 formed between the adjacentinsulating layers larger than that in the semiconductor memory accordingto the comparative example.

As a result, the semiconductor memory 1 according to the embodimentsuppresses an increase in the wiring resistance of the stacking wiresprovided in the memory cell array 10 and reduces the resistance value ofthe word lines, for example. In addition, the semiconductor memory 1according to the embodiment suppresses power consumption with a decreasein the wiring resistance.

For example, the resistance value of the conductive parts 51 (forexample, titanium nitride TiN) is higher than the resistance value ofthe conductive parts 52 (for example, tungsten W). Accordingly, even inthe case where the block insulating films 36 are included in the memorypillars MP in the comparative example, the semiconductor memory 1according to the embodiment has the low-resistance conductive parts 52larger in volume than those in the comparative example to make thewiring resistance of the word lines WL and the like lower than that inthe comparative example.

Other advantageous effects of the semiconductor memory 1 according tothe embodiment will be listed below.

In the comparative example described above, in the etching process inwhich to remove the sacrificial members corresponding to the word linesWL via the slits SLT, the time during which the block insulating films35 are immersed in an etching solution varies depending on the distancefrom the slit SLT. Specifically, the timing at which the sacrificialmembers are removed from a region distant from the slit SLT (forexample, the region between the memory pillars MP) is lagged behind thetiming at which the sacrificial members near the slit SLT are removed.

As a result, the time during which the block insulating films 35 formednear the slit SLT are immersed in an etching solution becomes longerthan the time during which the block insulating films 35 formed in theregion distant from the slit SLT are immersed in an etching solution. Inthe step of removing the sacrificial members, the etching solution isselected such that the etch selectivity of the sacrificial members ishigher than that of the block insulating films 35. However, depending onthe length of the time for immersion in the etching solution and theetch selectivity, the thickness of the block insulating films 35 mayvary corresponding to the distance from the slit SLT.

In contrast to this, in the semiconductor memory 1 according to theembodiment, the block insulating films 36 are formed in the memory holesMH. Further, at the formation of the conductive parts 52 using the slitsSLT, the block insulating films 36 are surrounded by the single-annularconductive parts 50 and 51 (the metal films 69) as illustrated in FIGS.6 and 7 and thus the side surfaces of the block insulating films 36 arenot immersed in the etching solution.

Accordingly, in the semiconductor memory 1 according to the embodiment,it is possible to suppress variations in the thicknesses of the blockinsulating films 35 and 36 included in the plurality of memory pillarsMP as compared to the semiconductor memory according to the comparativeexample.

As a result, the semiconductor memory 1 according to the embodiment cansuppress characteristic variations among the memory pillars MP ascompared to the semiconductor memory according to the comparativeexample, thereby improving the reliability of data stored in thesemiconductor memory 1.

FIG. 30 illustrates an example of an electric field applied to thememory pillar MP at the time of a writing action of the semiconductormemory 1. As illustrated in FIG. 30, in the semiconductor memory 1according to the embodiment, the convex portions CV can be formed on thesemiconductor 31 in the layer with the word line WL.

For example, when a high voltage is applied to the word line WL at thetime of a writing action, an electric field can concentrate on theconvex portions CV of the semiconductor 31. When electric fieldconcentration occurs as illustrated in the drawing, the potentialdifference between the channel and the charge accumulation layer (theinsulating film 34) in the corresponding memory cell transistor MTbecomes larger. As a result, in the semiconductor memory 1 according tothe embodiment, it is possible to improve the writing efficiency andincrease the speed of a writing action.

[1-4] Modification Example of the Embodiment

In the semiconductor memory 1 according to the embodiment describedabove, in the manufacturing process described with reference to FIG. 23,the etch selectivity of the water solution used for the removal of thesacrificial members 67 is higher in the conductive parts 51 than in theconductive parts 50, and thus the conductive parts 51 may not be left,for example. A structure and advantageous effects of a semiconductormemory 1 according to a modification example of the embodiment will bedescribed below.

FIG. 31 illustrates an example of a cross-section structure of a memorycell array 10 included in the semiconductor memory 1 according to themodification example of the embodiment. As illustrated in FIG. 31, thememory cell array 10 in the modification example is structured withoutthe conductive parts 51 as compared to the cross-section structure ofthe memory cell array 10 in the embodiment.

For example, spaces (cavities) SP are provided in regions without theconductive parts 51. The spaces SP are in contact with the convexportions TP of the memory pillar MP. In other words, the spaces SP are apair of spaces SP that is provided to sandwich the conductive part 50along the Z direction, for example, between the block insulating film 36in the memory pillar MP and the conductive part 52. That is, the spacesSP are included in portions between the block insulating film 36 in thememory pillar MP and the conductive part 52. The size of the spaces SPvaries depending on the size of the region with the conductive part 52.The spaces SP may also be called air gaps.

In this manner, in the semiconductor memory 1 according to themodification example of the embodiment, the spaces SP are provided nearthe outer periphery of the memory pillar MP. In a cross section parallelto the surface of the semiconductor substrate 20 and including the spaceSP, the distance between the center of the memory pillar MP and theportion of the space SP in contact with the memory pillar MP that ismost distant from the memory pillar MP is shorter than half the distance(MP pitch) between the centers of the adjacent memory pillars MP.

FIG. 32 is a cross-sectional view of FIG. 31 taken along lineXXXII-XXXII, illustrating an example of a structure of the memory pillarMP in the cross section parallel to the surface of the semiconductorsubstrate 20 and including the space SP.

As illustrated in FIG. 32, the structure of the memory pillar MP in thelayer including the space SP is similar to the structure of the memorypillar MP described with reference to FIG. 6. The space SP surrounds theside surface of the block insulating film 36. The conductive part 52surrounds the space SP. In other words, the space SP is provided betweenthe conductive part 52 and the block insulating film 36.

FIG. 33 illustrates an example of a process of formation of theconductive parts 52 in the wiring replacement process using the slit SLTin the semiconductor memory 1 according to the modification example ofthe embodiment.

As illustrated in FIG. 33(1), in the modification example of theembodiment, the conductive parts 51 are also removed at the time ofremoval of the sacrificial members 67 via the slit SLT. This can occurby lengthening the time for etching in this step, for example.

Next, the selective growth of the conductive parts 52 is executed basedon a metal material included in the conductive parts 50. In this step,the conductive parts 52 re-grow from the side surfaces of the conductiveparts 50 as illustrated in FIG. 33(2). In the process of the re-growth,the conductive parts 52 are also formed in the spaces where theconductive parts 51 would be formed in the embodiment.

The speed of formation of the conductive parts 52 varies depending onthe ease of attachment of a gas supplied via the slit SLT. Accordingly,as illustrated in FIG. 33(3), the grown conductive parts 52 are incontact with the insulating layers adjacent to the wiring layers to formthe spaces SP. In the subsequent steps, no gas is supplied to the spacesSP and thus the re-growth process proceeds with the spaces SP left.

As the process proceeds, the grown conductive part 52 reaches near theopening portion OP, for example, and the grown conductive parts 52between the adjacent memory pillars MP are in contact with each other asillustrated in FIG. 33(4). Accordingly, in the modification example ofthe embodiment, the spaces where the sacrificial members 67 were onceformed are filled with the grown conductive parts 52 and the spaces SPare left on the side surfaces of the memory pillars MP, for example.

In the semiconductor memory 1 according to the modification example ofthe embodiment described above, the volume of the conductive parts 52 islarger than that in the semiconductor memory 1 according to theembodiment, for example. Since the resistance value of the conductiveparts 52 is lower than that of the conductive parts 51, thesemiconductor memory 1 according to the modification example of theembodiment allows the wiring resistance of the word lines WL and othersto be reduced as compared to that in the semiconductor memory 1according to the embodiment.

In addition, the spaces SP adjacent to the memory pillars MP areeffective in suppressing a fringe effect. Therefore, the semiconductormemory 1 according to the modification example of the embodiment cansuppress interference between the adjacent memory cell transistors MT toimprove the reliability of data stored.

The conductive parts 51 are completely removed from the semiconductormemory 1 according to the modification example of the embodimentdescribed above, but the semiconductor memory 1 is not limited to this.For example, in the semiconductor memory 1 according to the modificationexample of the embodiment, the conductive parts 51 may be left near thespaces SP.

[2] Other Modification Examples

A semiconductor memory according to an embodiment includes a firstconductor, a first insulator and a plurality of memory pillars. Thefirst conductor and the first insulator are alternately stacked along afirst direction. The plurality of memory pillars penetrates through thestacked first conductor and first insulator. Each of the memory pillarsinclude a semiconductor along the first direction, a tunnel insulatingfilm that surrounds a side surface of the semiconductor, a secondinsulator that surrounds a side surface of the tunnel insulating film,and a block insulating film that surrounds a side surface of the secondinsulator. The memory pillars include a first memory pillar. The stackedfirst insulator includes a first layer and a second layer that areadjacent to each other in the first direction. The first conductorbetween the first layer and the second layer includes a first conductivepart, a second conductive part, and a first dissimilar conductive part.The first conductive part is in contact with the first layer and thesecond layer and widens along a second direction crossing the firstdirection. The second conductive part is provided between a blockinsulating film of the first memory pillar and the first conductivepart, is in contact with the block insulating film and the firstconductive part, and is formed from the same material as for the firstconductive part. The first dissimilar conductive part is a pair ofconductive parts that sandwiches the second conductive part along thefirst direction between the block insulating film of the first memorypillar and the first conductive part, and is formed from a materialdifferent from the material for the first conductive part and the secondconductive part. Thereby, the semiconductor memory 1 can reduce aresistance value of the word line WL in the semiconductor memory 1.

Accordingly, in the semiconductor memory according to the embodiment, itis possible to reduce the wiring resistance of the word lines andothers.

The memory pillars MP may be structured such that a plurality of pillarsis coupled together in the Z direction. For example, the memory pillarsMP may be structured such that a pillar penetrating through theconductor 24 (the select gate line SGD) and a pillar penetrating throughthe plurality of conductors 23 (the word lines WL) are coupled together.The memory pillars MP may be structured such that a plurality of pillarspenetrating through the plurality of conductors 23 is coupled togetherin the Z direction.

In the embodiment, the slits SLT divide the conductors 22 to 24.However, the slits SLT may not divide the conductor 24. In this case,the memory pillars MP are structured such that a plurality of pillars iscoupled together in the Z direction, and the pillar provided on thelower side penetrates through the conductors 22 and 23, and the pillarprovided on the upper side penetrates through the conductor 24. Theconductor 24 is divided by a slit different from the slit SLT, forexample, and each of the plurality of divided conductors 24 serves asselect gate line SGD.

In the embodiment, the semiconductor memory 1 is structured such that acircuit such as the sense amplifier module 16 is provided under thememory cell array 10 as an example. However, the semiconductor memory 1is not limited to this. For example, the semiconductor memory 1 may bestructured such that the memory cell array 10 and the sense amplifiermodule 16 are adjacent to each other on the semiconductor substrate 20in a direction parallel to the surface of the semiconductor substrate20. In this case, in each of the memory pillars MP, the semiconductor 31and the source line SL are electrically connected via the bottom surfaceof the memory pillar MP, for example.

The memory cell array 10 may be structured in other ways. Anotherstructure of the memory cell array 10 is described in the U.S. patentapplication Ser. No. 12/407,403 titled “THREE-DIMENSIONAL STACKEDNONVOLATILE SEMICONDUCTOR MEMORY” and filed on Mar. 19, 2009, forexample. Still other structures of the memory cell array 10 aredescribed in the U.S. patent application Ser. No. 12/406,524 titled“THREE-DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY” and filedon Mar. 18, 2009 and in the U.S. patent application Ser. No. 12/679,991titled “NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHODTHEREOF” and filed on Mar. 25, 2010. Further another structure of thememory cell array 10 is described in the U.S. patent application Ser.No. 12/532,030 titled “SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURINGTHE SAME” and filed on Mar. 23, 2009. These patent applications areentirely incorporated herein by reference.

The term “connection” herein refers to electrical connection and doesnot exclude the intervention of another element between electricallyconnected components, for example.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A semiconductor memory comprising: a firstconductor and a first insulator that are alternately stacked along afirst direction; and a plurality of memory pillars that penetratesthrough the stacked first conductor and first insulator, each of thememory pillars including a semiconductor along the first direction, atunnel insulating film that surrounds a side surface of thesemiconductor, a second insulator that surrounds a side surface of thetunnel insulating film, and a block insulating film that surrounds aside surface of the second insulator, wherein the memory pillars includea first memory pillar, the stacked first insulator includes a firstlayer and a second layer that are adjacent to each other in the firstdirection, the first conductor between the first layer and the secondlayer includes a first conductive part and a second conductive part, thefirst conductive part is in contact with the first layer and the secondlayer and widens along a second direction crossing the first direction,the second conductive part is provided between a block insulating filmof the first memory pillar and the first conductive part, is in contactwith the block insulating film and the first conductive part, and isformed from the same material as for the first conductive part, and aportion between the block insulating film of the first memory pillar andthe first conductive part includes a space.
 2. The memory of claim 1,wherein the memory pillars further include a second memory pillaradjacent to the first memory pillar, and in a cross section parallel toa surface of a substrate and including the space, a first distancebetween a center of the first memory pillar and a portion of the spacemost distant from the first memory pillar is shorter than half a seconddistance between the center of the first memory pillar and a center ofthe second memory pillar.
 3. The memory of claim 1, wherein the memorypillars further include a second memory pillar adjacent to the firstmemory pillar, the first conductor between the first layer and thesecond layer further includes a third conductive part, the thirdconductive part is provided between a block insulating film of thesecond memory pillar and the first conductive part, is in constant withthe block insulating film of the second memory pillar and the firstconductive part, and is formed from the same material as for the firstconductive part, and the first conductive part includes a seam along thefirst direction between the first memory pillar and the second memorypillar.
 4. The memory of claim 1, further comprising: an insulation partthat is provided in a slit extending along a third direction crossingthe first direction and dividing the stacked first conductor and firstinsulator, and is in contact with the first conductive part, wherein nomemory pillar is included between the first memory pillar and theinsulation part, and no seam is included in the first conductive partbetween the first memory pillar and the insulation part.
 5. The memoryof claim 1, wherein a boundary is formed between the first conductivepart and the second conductive part.
 6. The memory of claim 1, whereinthe block insulating film of the first memory pillar includes a portionsandwiched between the first layer and the second layer.
 7. The memoryof claim 1, wherein the block insulating film includes a cylinder-shapedfirst oxide along the first direction and a second oxide different fromthe first oxide along the first direction, and the second oxidesurrounds a side surface of the first oxide.
 8. The memory of claim 1,wherein the second conductive part is provided in a single-annular form.9. The memory of claim 1, wherein each of the first conductive part andthe second conductive part includes tungsten.